`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   16:56:11 05/04/2013
// Design Name:   Compare
// Module Name:   T:/Lab3/tb_compare.v
// Project Name:  Lab3
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: Compare
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module tb_compare;

	// Inputs
	reg [N - 1 : 0] a_in;
	reg [N - 1 : 0] b_in;

	// Outputs
	wire [(2 * N) - 1: 0] d_out;

	// Instantiate the Unit Under Test (UUT)
	Compare #(.N(4)) uut (
		.a_in(a_in), 
		.b_in(b_in), 
		.d_out(d_out)
	);
	
	parameter N = 4;

	initial begin
		// Initialize Inputs
		a_in = 0;
		b_in = 0;

		// Wait 100 ns for global reset to finish
		#100;
        
		// Add stimulus here
		a_in <= 4'h5;
		b_in <= 4'h5;
		
		#100;
		
		b_in <= 4'h6;
		
		#100;
		
		a_in <= 4'h6;
		
		#100
		
		a_in <= 4'h7;

	end
      
endmodule

